1. Field of the Invention
The present invention relates to a microcomputer using a basic clock stop instruction (called the STP instruction hereunder) to execute debug-dedicated interruption (called debug interruption hereunder) whereby a program under development (called the user program hereunder) is debugged.
2. Description of the Prior Art
Heretofore, microcomputers for which a user program was being developed were provided with an interrupt circuit including a debug interrupt request generating circuit for debugging the program in question. Debug interrupt requests were issued illustratively by an externally furnished program debugger (called the external debugger hereunder) to interrupt user program execution for debug interrupt handling.
FIG. 1 is a block diagram showing how a conventional microcomputer is connected to an external debugger. In FIG. 1, reference numeral 1 stands for a microcomputer and 2 for an external debugger. Inside the microcomputer 1, reference numeral 10 is a central processing unit (CPU); 11 is an address bus; 12 is a data bus; 13 is a control signal line; 14 is a random access memory (RAM); 15 is a program memory; 16 is an interrupt control circuit; 17 is a debug support circuit; 18 is an interrupt request signal line over which a interrupt request signal is transmitted; and 19 is a debug bus.
FIG. 2 is a block diagram depicting an internal structure of the debug support circuit 17 inside the microcomputer 1. In FIG. 2, reference numeral 20 represents a trace circuit that outputs onto the debug bus 19 the run state of the CPU 10, i.e., the status of the address bus 11, data bus 12 and control signal line 13. Reference numeral 21 denotes a register to and from which data may be written and read by the external debugger 2 and by the CPU 10 of the microcomputer 1.
The microcomputer 1 of the above constitution works as follows:
Suppose that the microcomputer 1 is executing a user program stored in the program memory 15. In that case, the external debugger 2 reads trace data from the debug support circuit 17 of the microcomputer 1 over the debug bus 19, whereby the workings of the CPU 10 in the microcomputer 1 are monitored. When the effective address of the trace data in the CPU 10 has illustratively reached a predetermined address value, the external debugger 2 outputs an interrupt request signal onto the interrupt request signal line 18. Upon receipt of the interrupt request signal, the microcomputer 1 halts temporarily the current user program execution to carry out debug interrupt handling. With debug interrupt handling initiated, the CPU 10 performs a debug handling program held in the program memory 15 and communicates with the external debugger 2 via the register 21 of the debug support circuit 17.
Illustratively, after issuing the debug interrupt request, the external debugger 2 communicates with the CPU 10 through the register 21 of the debug support circuit 17 to know the register contents in the microcomputer 1 as well as the contents of the RAM 14. Debug interrupt requests are handled in the same manner as ordinary interrupt requests. That is, on accepting an interrupt request, the CPU 10 saves the program counter value (i.e, program counter contents) indicating what should be executed next into a memory area pointed to by a stack pointer (the area is generally allocated in the RAM 14). Then interrupt handling is carried out. At the end of the handling, an interrupt return instruction (called the RTI instruction hereunder) is executed whereby the program counter value in effect at the start of the interruption is read from the memory area designated by the stack pointer for transfer to the program counter. In the manner described, the user program is first interrupted by a debug interrupt request, the request is then handled appropriately, and the temporarily halted user program execution is resumed from the instruction next to the interrupted program instruction.
Debug interruption initiated by an interrupt request signal sent from the external debugger 2 over the interrupt request signal line 18 halts user program execution temporarily for debug handling. Generally, arrangements are made so that the debug interrupt handling time per request is sufficiently short so as not to hinder user program execution. For example, where memory contents in the microcomputer 1 are to be retrieved by the external debugger 2, the address range of the memory is divided into a plurality of portions so that each pass of debug interrupt handling will involve retrieving memory contents of only several addresses and will be finished over a sufficiently short period of time.
It should be noted that even where the STP instruction is executed to stop the basic clock inside the microcomputer 1, a debug interrupt request when issued cancels the STP instruction in order to perform debug interrupt handling. This means that upon return to the user program following execution of the RTI instruction, processing is resumed from the instruction next to the STP instruction in accordance with the program counter value which was saved upon interrupt initiation and which is retrieved from the memory area pointed to by the stack pointer.
The above-mentioned conventional techniques related to microcomputers are described illustratively by JP-A Nos. Sho 58-205226, Hei 5-73349, Sho 62-95644, and Hei 1-250143.
As described, conventional microcomputers suffer from the problem of the STP instruction getting canceled by an unintended event, i.e, by debug interrupt handling while a program is being debugged. For the external debugger 2 to circumvent the above problem requires performing three steps:
(1) Disassemble the program execution address portion in effect when a debug interrupt request is accepted, and search for an STP instruction. PA0 (2) Match analyzed trace data with the outcome of the disassembly to verify whether any STP instruction has been carried out. PA0 (3) If the STP instruction is judged to have been executed, decrement the program counter value saved into the memory area pointed to by the stack pointer at the time of debug interrupt initiation, thereby obtaining the address at which to execute the STP instruction upon completion of the current debug interruption.
Carrying out the additional steps above prolongs the time required to perform debug interrupt handling per request.